第一阶段
高速PCB设计中的理论基础
传输线理论、信号完整性（反射、串扰、过冲、地弹、振铃等）、电磁兼容性和时序匹配等等。
2 SPECCTRAQuest设计流程
2.1 Pre-Placement
2.2 Board Setup Requirements for Extracting and Applying Topologies
2.3 Database Setup Advisor
—Cross-Section
—DC Nets
—DC Voltages
—Device Setup . ??—SI Models
—SI Audit
3 拓扑结构的抽取与仿真 Extracting and Simulating Topologies
3.1 Pre-Route Extraction Setup—Default Model Selection.
3.2 Pre-Route Extraction Setup—Unrouted Interconnect
3.3 Pre-Route Template Extraction
3.4 SQ Signal Explorer Expert
3.5 Analysis Preferences
3.6 SigWave
3.7 Delay Measurements
第二阶段
4 确定和施加约束 Determining and Adding ConstraintsSolution
4.1 Solution SpaceAnalysis: Step 1 to 6
4.2 Parametric Sweeps.
4.3 Constraints :
Topology Template Constraints
Switch/Settle Constraints
Assigning the Prop Delay Constraints
Impedance Constraint
Relative Propagation Delay Constraint
Diff Pair Constraints
Max Parallel Constraint
Wiring Constraint
User-Defined Constraint
Signal Integrity Constraints
4.4 Usage of Constraints Defined in Topology Template
5 模板应用和基于约束的布局
Template Applications and Constraint-Driven Placement
5.1 Creating a Topology
5.2 Wiring the Topology
5.3 TLines and Trace Models
5.4 Coupled Traces
5.5 RLGC Matrix of Coupled Trace Models
5.6 Crosstalk Simulation in SQ Signal Explorer Expert
5.7 Simulating with Coupled-Trace Models
5.8 Sweep Simulation Results with Coupled-Trace Models
5.9 Extracting a Topology Using the Constraint Manager
5.10 Electrical Constraint Set
5.11 Applying Electrical CSet
5.12 Worksheet Analysis
5.13 Spacing and Physical Rule Sets
5.14 Electrical Rule Set
第三阶段
6 基于约束的布线 Constraint-Driven Routing
6.1 Manual Routing
6.2 Routing with the SPECCTRA Smart Route
6.3 Driving Constraints in Routing
7 布线后的DRC检查和分析 Post-Route DRC and Analysis
7.1 Post-Route Analysis
7.2 SigNoise
7.3 Reflection Simulation
7.4 Reflection Waveform Analysis
7.5 Comprehensive Simulation
7.6 Crosstalk Simulation
7.7 Crosstalk Analysis
7.8 Simultaneous Switching Noise Simulation
7.9 SSN Waveform Analysis
7.10 System-Level Analysis
7.11 A Complete Design Link
7.12 Initialize Design Link
8 差分信号设计 Differential Pair Design Exploration
8.1 Types of Differential Pairs in SPECCTRAQuest
8.2 Create Differential Pair Using SPECCTRAQuest
8.3 Create Differential Pair Using Constraint Manager
8.4 Assigning Differential Pair Signal Models
8.5 Preference to Extract Unrouted Differential Pair Topology
8.6 Extracting Unrouted Differential Pair Topology
8.7 Custom Stimulus to Analyze Differential Pair Topology
8.8 Differential Pair Topology Analysis
8.9 Coupled Trace Model and Differential Pair Topology
8.10 Layout Cross-section Editor
8.11 Differential Pair Constraints
8.12 Differential Pair Constraints in the Constraint Manager
8.13 Differential Pair Analysis in the Constraint Manager
8.14 Post Route Extraction
9 时序仿真和和PI仿真
9.1 时序仿真
9.2 PI仿真
第四阶段
10. 多板仿真和Design Link模型
10.1 Design Link模型的创建和修改
10.2 主板和子板，底板和核心板的接口信息的查找和显示
10.3 多板仿真建模
10.4 多板仿真主板和子板资源添加和接口连接
10.5 网络列表创建
10.6 仿真参数设置
10.7 探测仿真
11. SI仿真环境的建立和时序仿真－－DDR3和Flash,高速数据线的时序控制
11.1 SI仿真模型的查找技巧和IBIS格式转换
11.2 仿真环境的设置和仿真模型分配和审核
11.3 DDR3和Flash,高速数据线时序仿真在项目开发中作用和意义
11.4 时序控制的公式推导和理论基础
11.5 对应 Setup Time和 Hold Time 公式的深入理解
11.6 公式参数在芯片datasheet中的查找
11.7 时序仿真的高速数据线等网络组的创建和拓扑提取
11.8 时序仿真的激励
11.9 时序仿真类型
11.10 时序仿真结果查看
11.11 时序仿真的约束
11.12 SigXplore和Constraint Manager
11.13 设计规则应用和规则驱动布局
12. 差分仿真
12.1 差分线仿真模型
12.2 差分线定义
12.3 差分线仿真设计技巧
12.4 如何在Constraint Manager中识别和查找差分对
12.5 如何建立差分对
12.5 差分对拓扑提取和仿真
12.6 SigXplore中差分线约束
12.7 差分约束更新到约束管理器
13.PI电源完整性仿真
13.1 电源平面对的耦合和去耦
13.2 电源仿真的环境搭建
13.3 阻抗控制和层叠结构设计
13.4 电源平面对构建中各种复杂情况的考虑和处理原则
13.5 PI电源完整性仿真参数设置
13.5 EMI/EMI 处理
13.6 电压调节模块和噪声源
13.7 仿真中电容的选取
13.8 多节点仿真
13.9 波形图的处理
14. 后仿真－布线后分析
14.1 反射仿真
14.2 串扰仿真
14.3 同步开关噪声仿真
14.4 寄生仿真
14.5 EMI仿真
14.6 振铃仿真
15. 自动和手动布线的技巧
15.1 自动布线技巧
15.2 手动布线技巧 |
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