集成电路设计中心 企业 曙海嵌入式 就业培训基地长期班 就业培训基地长期班

客户常见疑问解答 手机阅读模式
嵌入式培训
嵌入式Linux就业班马上开课了 详情点击这儿

免费报名电话薪水倍增计划
上海:021-51875830
北京:010-51292078
深圳:4008699035
武汉:027-50767718
成都:4008699035
南京:4008699035
广州:4008699035
西安:029-86699670
石家庄:4008699035
免费报名电话
曙海研发与生产请参见网址:
www.shanghai66.cn 新版网站
全英文授课课程(Training in English)
   
  首 页  培训新动态  课程介绍   培训报名  企业培训  付款方式  讲师介绍 学员评价 关于我们  联系我们  承接项目 开发板商城  就业  网校
嵌入式协处理器--FPGA
FPGA项目实战系列课程----
嵌入式OS--4G手机操作系统
嵌入式协处理器--DSP
手机/网络/动漫游戏开发
嵌入式OS-Linux
嵌入式CPU--ARM
嵌入式OS--WinCE
单片机培训
嵌入式硬件设计
Altium Designer Layout高速硬件设计
嵌入式OS--VxWorks
PowerPC嵌入式系统/编译器优化
PLC编程/变频器/数控/人机界面 
开发语言/数据库/软硬件测试
3G手机软件测试、硬件测试
芯片设计/大规模集成电路VLSI
云计算、物联网
开源操作系统Tiny OS开发
小型机系统管理
其他类
WEB在线客服
南京WEB在线客服
武汉WEB在线客服
西安WEB在线客服
广州WEB在线客服
点击这里给我发消息  
QQ客服一
点击这里给我发消息  
QQ客服二
点击这里给我发消息
QQ客服三
专家讲师

 曙海--工程师的项目导师。

曙海讲师体系和课程体系历经多年升级,形成了以项目实战经验丰富的工程师为基础,产学研相结合的体系,曙海的学员大部分来自外资企业、上市公司的,研究所的工程师或高校老师,很多学员都参加工作很多年了,这对曙海的讲师形成很高的要求,曙海的讲师队伍名校博士、硕士学历的工程师占绝大多数,他们大部分为上海贝尔,TI德州仪器,华为,中科院,中兴,Xilinx,Intel英特尔,NI公司,Cadence公司,Synopsys,IBM,Altera,Oracle,synopsys,微软,飞思卡尔等大型公司高级工程师,项目经理,技术支持专家,他们有着深厚的专业技能和技术素养,丰富的项目实战经验,基本上都有十多年实际项目经验,开发过多个大型项目。

 针对客户实际需求,案例教学,边讲边练,互动式授课,曙海的专家讲师以专业、敬业的精神,倾囊相授,不辜负每个学员的托付和期望。

良心教育--用良心做培训,以技术赢得客户尊重!

更多专家讲师,请点击此处查看。

曙海特色

曙海--IT高端培训的良心技术服务机构,一站式软硬件技术服务平台。

包教包会,免费重修!全国连锁,线上、线下培训,公开课,上门内训,技术咨询,承接项目,专家外包。特殊技术订制培训&咨询,按实际需求服务,课程不受时间限制(工作日、周末、晚班),充足的专家资源(每门课对应多名专家),精确匹配服务,不受地点限制--全国连锁。小班教学,丰富专家资源,顾问式咨询服务。

以项目实战为导向,以实战演练贯穿始终,练习!练习!直到把技术练习到血液中!

更多培训特色介绍,请点击此处查看。

公益培训通知与资料下载
企业招聘与人才推荐(免费)

合作企业新人才需求公告

◆招人、应聘、人才合作,
请把需求发到officeoffice@126.com或
访问曙海旗下网站---
电子人才网
www.morning-sea.com.cn
合作伙伴与授权机构
现代化的多媒体教室
曙海招聘启示
邮件列表
 
 
  RTL Synthesis(Design Synthesis)培训
   班级规模及环境--热线:4008699035 手机:15921673576/13918613812( 微信同号)
       坚持小班授课,为保证培训效果,增加互动环节,每期人数限3到5人。
现场面授
   上课时间和地点
上课地点:【上海】:同济大学(沪西)/新城金郡商务楼(11号线白银路站) 【深圳分部】:电影大厦(地铁一号线大剧院站)/深圳大学成教院 【北京分部】:北京中山/福鑫大楼 【南京分部】:金港大厦(和燕路) 【武汉分部】:佳源大厦(高新二路) 【成都分部】:领馆区1号(中和大道) 【沈阳分部】:沈阳理工大学/六宅臻品 【郑州分部】:郑州大学/锦华大厦 【石家庄分部】:河北科技大学/瑞景大厦 【广州分部】:广粮大厦 【西安分部】:协同大厦
近开课时间(周末班/连续班/晚班)
RTL Synthesis(Design Synthesis)培训:2024年10月14日......(欢迎您垂询,视教育质量为生命!)
   实验设备
     ☆资深工程师授课

        
        ☆注重质量
        ☆边讲边练

        ☆合格学员免费推荐工作

        

        专注高端培训17年,曙海提供的课程得到本行业的广泛认可,学员的能力
        得到大家的认同,受到用人单位的广泛赞誉。

        ★实验设备请点击这儿查看★
   新优惠
       ◆在读学生凭学生证,可优惠500元。

        本课程实战演练使用Synopsys公司的DC,PT等工具,
和Cadence公司的Encounter,Virtuoso等工具,多工具联合从头至尾强化练习整个芯片的生成过程,强调实战,实战,还是实战!

        免费、无保留赠送,教学过程中使用的Synopsys公司和Cadence公司的全套工具和安装方法,而且还赠送已经在VMware Linux下安装好的Synopsys公司和Cadence公司的全套工具(这套工具非常珍贵,费了老师很多心血才全部安装好),让您随时随地,打开电脑就能进行芯片的设计和练习!

IC工具虚拟机
   质量保障

        1、培训过程中,如有部分内容理解不透或消化不好,可免费在以后培训班中重听;
        2、课程完成后,授课老师留给学员手机和Email,保障培训效果,免费提供半年的技术支持。
        3、培训合格学员可享受免费推荐就业机会。

  RTL Synthesis(Design Synthesis)培训
培训方式以讲课和实验穿插进行

课程描述:

第一阶段 Design Compiler 1

Overview
This course covers the ASIC synthesis flow using Design Compiler Topographical / Graphical -- from reading in an RTL design (Verilog, SystemVerilog and VHDL) to generating a final gate-level netlist. You will learn how to read in your design file(s), specify your libraries and physical data, constrain a complex design for timing and floorplan, apply synthesis techniques using Ultra, compile to achieve timing closure and an acceptable congestion, analyze the synthesis results for timing and congestion, and generate output data that works with downstream layout tools.

You will verify the logic equivalence of synthesis transformations (such as Datapath optimizations and Register Retiming) to that of an RTL design using Formality. The course includes labs to reinforce and practice key topics discussed in lecture. All the covered commands and flows are printed separately in a 5-page Job Aid, which you can refer to back at work.

Objectives
At the end of this workshop the student should be able to:
  • Create a setup file to specify the libraries and physical data
  • Read in a hierarchical design
  • Constrain a complex design for timing, taking into account different environmental attributes such as output loading, input drive strength, process, voltage and temperature variations, as well as post-layout effects such as clock skew
  • Constrain multiple (generated) clocks considering Signal integrity analysis
  • Execute the recommended synthesis techniques to achieve timing closure
  • Analyze and Improve global route congestion
  • Perform test-ready synthesis
  • Verify the logic equivalence of a synthesized netlist compared to an RTL design
  • Write DC-Tcl scripts to constrain designs, and run synthesis
  • Generate and interpret timing, constraint, and other debugging reports
  • Understand the effect that RTL coding style can have on synthesis results
  • Generate output data (netlist, constraints, scan-def) that works with downstream physical design or layout tools

Course Outline

Unit 1
  • Introduction to Synthesis
  • Design and Technology Data
  • Design and Library Objects
  • Timing Constraints

Unit 2
  • Environmental Attributes
  • Synthesis Optimization Techniques
  • Timing Analysis

Unit 3
  • Additional Constraint Options
  • Multiple Clocks and Timing Exceptions
  • Congestion Analysis and Optimization
  • Post-Synthesis Output Data
  • Conclusion



第二阶段 Design Compiler 2: Low Power

Overview
At the end of this one day, seminar based, workshop you will understand how to apply both traditional and UPF based power optimization techniques during RTL synthesis and scan insertion:

For single voltage designs, you will learn how to apply the 2 traditional power optimization techniques of clock gating and leakage power recovery, optimizing for dynamic power and leakage power respectively.

For multi-voltage or multi-supply designs, you will learn how to apply the IEEE 1801 UPF flow that uses a power intent specification which is applied to RTL designs. You will understand how to synthesize RTL designs for the required power intent and power-optimization requirements using top-down vs. hierarchical UPF methodologies. You will also learn how to insert scan chains to the synthesized netlist ensure that the gate level design does not have any multi-voltage violations, before writing out design data for Place and Route.

Objectives

At the end of this workshop the student should be able to:

  • Apply clock gating to a design at the RTL and gate level
  • Perform multi-stage, hierarchical, and power driven clock gating
  • Perform leakage optimization using multi Vt libraries
  • Restrict the usage of leaky cells
  • Specify power intent using UPF
  • Demonstrate flexible isolation strategy in UPF 2.0
  • Check for UPF readiness of library, reporting PG pins
  • State the purpose of SCMR attribute in library
  • Recognize tradeoff when using dual vs. single rail special cells
  • Correctly specify PVT requirements
  • State how the 6 special cells are synthesized
  • Describe supply net aware Always on Synthesis
  • Apply 2 key debugging commands in a UPF flow
  • Control voltage, power domain mixing when inserting scan chains
  • Allow/prevent the reuse of level shifters and isolation cells between scan and functional paths
  • Minimize toggle in functional logic during scan shifting
  • Validate SCANDEF information for place and route

Course Outline

  • Clock Gating
  • Leakage Power Optimization
  • Power Intent using IEEE 1801 UPF
  • Library Requirements
  • Synthesis with UPF
  • Power Aware DFT



第三阶段 DFT Compiler

Overview
In this workshop you will learn to use DFT Compiler to perform RTL and gate-level DFT rule checks, fix DFT DRC rule violations, and to insert scan using top-down and bottom-up flows. The workshop explores essential techniques to support large, multi-million gate SOC designs including the bottom-up scan insertion flow in the logical (Design Compiler) domain. Techniques learned include: performing scan insertion in a top-down flow; meeting scan requirements for number of scan chains, maximum chain length and reusing functional pins for scan testing, inserting an On-Chip Clocking (OCC) controller for At-Speed testing using internal clocks; and using Adaptive Scan (DFTMAX) to insert additional DFT hardware to reduce the test time and the test data volume required for a given fault coverage.

Objectives
At the end of this workshop the student should be able to:
  • Create a test protocol for a design and customize the initialization sequence, if needed, to prepare for DFT DRC checks
  • Perform DFT DRC checks at the RTL, pre-DFT, and post-DFT stages
  • Recognize common design constructs that cause typical DFT violations
  • Automatically correct certain DFT violations at the gate level using AutoFix
  • Implement top-down scan insertion flow achieving well-balanced scan chains
  • Write a script to perform all the steps in the DFT flow, including exporting all the required files for ATPG and Place & Route
  • Develop a bottom-up scan insertion script for full gate-level designs to use Test Models at the top-level to improve capacity and runtime
  • Insert an On-Chip Clocking (OCC) controller to use for At-Speed testing with internal clocks
  • Modify a scan insertion script to include DFT-MAX Adaptive Scan compression

Course Outline

Unit 1
  • Introduction to Scan Testing
  • DFT Compiler Flows and Setup
  • Test Protocol
  • DFT Design Rule Checks

Unit 2
  • DFT DRC GUI Debug
  • DRC Fixing
  • Top-Down Scan Insertion
  • Exporting Files

Unit 3
  • High Capacity DFT Flows
  • On-Chip Clocking (OCC)
  • Multi-Mode DFT
  • DFT MAX

曙海教育实验设备
fpga培训实验板
fpga培训实验
fpga图像处理
曙海培训实验设备
fpga培训班
 
本课程部分实验室实景
曙海实验室
实验室
曙海培训
曙海培训优势
 
版权所有:上海曙海信息网络科技有限公司 copyright 2000-2016
 
上海总部培训基地

地址:上海市云屏路1399号26#新城金郡商务楼310。
(地铁11号线白银路站2号出口旁,云屏路和白银路交叉口)
邮编:201821
热线:021-51875830 32300767
传真:021-32300767
业务手机:15921673576/13918613812
E-mail:officeoffice@126.com
客服QQ: shuhaipeixun
北京培训基地

地址:北京市昌平区沙河南街11号312室
(地铁昌平线沙河站B出口) 邮编:102200 行走路线:请点击这查看
热线:010-51292078
传真:010-51292078
业务手机:15701686205
E-mail:officeoffice@126.com
客服QQ:1243285887
深圳培训基地

地址:深圳市环观中路28号82#201室

热线:4008699035
传真:4008699035
业务手机:13699831341

邮编:518001
信箱:qianru2@51qianru.cn
客服QQ:2472106501
南京培训基地

地址:江苏省南京市栖霞区和燕路251号金港大厦B座2201室
(地铁一号线迈皋桥站1号出口旁,近南京火车站)
热线:4008699035
传真:4008699035
邮编:210046
信箱:qianru3@51qianru.cn
客服QQ:1325341129
 
成都培训基地

地址:四川省成都市高新区中和大道一段99号领馆区1号1-3-2903 邮编:610031
热线:4008699035 业务手机:13540421960
客服QQ:1325341129 E-mail:qianru4@51qianru.cn
武汉培训基地

地址:湖北省武汉市江岸区汉江北路34号 九运大厦401室 邮编:430022
热线:4008699035
客服微信:shuhaipeixun
E-mail:qianru5@51qianru.cn
广州培训基地

地址:广州市越秀区环市东路486号广粮大厦1202室

热线:4008699035
传真:4008699035

邮编:510075
信箱:qianru6@51qianru.cn
西安培训基地

地址:西安市雁塔区高新二路12号协同大厦901室

热线:029-86699670
业务手机:18392016509
传真:029-86699670
邮编:710054
信箱:qianru7@51qianru.cn
 
沈阳培训基地

地址:辽宁省沈阳市东陵浑南新区沈营路六宅臻品29-11-9 邮编:110179
热线:4008699035
E-mail:qianru8@51qianru.cn
郑州培训基地

地址:郑州市高新区雪松路锦华大厦401

热线:4008699035

邮编:450001
信箱:qianru9@51qianru.cn
石家庄培训基地

地址:石家庄市高新区中山东路618号瑞景大厦1#802

热线:4008699035
业务手机:13933071028
传真:4008699035
邮编:050200
信箱:qianru10@51qianru.cn
 

双休日、节假日及晚上可致电值班电话:4008699035 值班手机:15921673576/13918613812 或加qq:1299983702和微信:shuhaipeixun


备案号:沪ICP备08026168号

.(2014年7月11).......................................................................................
在线客服